Testing integrated circuits, has become both more difficult and more important as the complexity of the circuits has increased.
The amount of resources spent in conventional burn-in and functional margin testing accounts for a non-trivial fraction of chip manufacturing cost. Sending a chip through a thermal cycle and testing it with a highly expensive automated tester is an expense that can be avoided if the chip can be eliminated by a less expensive method.
In addition, there is a class of latent defects that do not show up as fatal flaws in a conventional test, but have a high probability of causing the chip to fail.
In the past, excessive current draw has been tested by applying a voltage to the module or chip through a resistor and measuring the voltage drop across the test resistor. This procedure requires extra wiring on the chip that consumes space.
Some circuits employ Built-In Self-Test modules (BIST) that consume silicon area but permit testing a number of chips simultaneously.
The art could benefit from a simple and inexpensive testing technique adapted to identify chips with a high probability of failing.